Wireless Network On-Chips History-Based Traffic Prediction for Token Flow Control and Allocation
DOI:
https://doi.org/10.11113/elektrika.v18n3.162Abstract
Wireless network-on-chip (WiNoC) uses a wireless backbone on top of the traditional wired-based NoC which demonstrated high scalability. WiNoC introduces long-range single-hop link connecting distanced core and high bandwidth radio frequency interconnects that reduces multi-hop communication in conventional wired-based NoC. However, to ensure full benefits of WiNoC technology, there is a need for fair and efficient Medium Access Control (MAC) mechanism to enhance communication in the wireless Network-on-Chip. To adapt to the varying traffic demands from the applications running on a multicore environment, MAC mechanisms should dynamically adjust the transmission slots of the wireless interfaces (WIs), to ensure efficient utilization of the wireless medium in a WiNoC. This work presents a prediction model that improves MAC mechanism to predict the traffic demand of the WIs and respond accordingly by adjusting transmission slots of the WIs. This research aims to reduce token waiting time and inefficient decision making for radio hub-to-hub communication and congestion-aware routing in WiNoC to enhance end to end latency. Through system level simulation, we will show that the dynamic MAC using an History-based prediction mechanism can significantly improve the performance of a WiNoC in terms of latency and network throughput compared to the state-of-the-art dynamic MAC mechanisms.
References
Mansoor, N. Robust and Traffic Aware Medium Access
Control Mechanisms for Energy-Efficient mm-Wave
Wireless Network-on-Chip Architectures. 2017.
Agyeman, M. O., Zong, W., Wan, J.-X., Yakovlev, A., Tong,
K. and Mak, T. Novel hybrid wired- wireless network-on-
chip architectures: Transducer and communication fabric
design. Proceedings of the 9th International Symposium on
Networks-on-Chip. ACM. 2015. 32.
Wang, C., Hu, W.-H. and Bagherzadeh, N. A wireless
network-on-chip design for multicore platforms. 2011 19th
International Euromicro conference on parallel, distributed
and network-based processing. IEEE. 2011. 409–416.
Ebrahimi, M. Adaptive Routing Approaches for
Networked Many-Core Systems. 2013.
Deb, S., Ganguly, A., Chang, K., Pande, P., Beizer, B. and
Heo, D. Enhancing performance of network-on-chip
architectures with millimeter wave wireless interconnects,
ASAP 2010-21st IEEE International Conference on
Application specific Systems, Architectures and Processors.
IEEE. 2010.
DiTomaso, D., Kodi, A., Kaya, S. and Matolak, D. iWISE:
Inter-router wireless scalable express channels for
network-on-chips (NoCs) architecture. High Performance
Interconnects (HOTI), 2011 IEEE 19th Annual Symposium
on. IEEE. 2011. 11–18.
Sikder, M. A. I. Emerging Technologies in On-Chip and
Off-Chip Interconnection Network. Ph.D. Thesis. Ohio
University, 2016.
Wang, S. and Jin, T. Wireless network-on-chip: A survey.
The Journal of Engineering, 2014(3): 98–104.
Mansoor, N., Vashist, A., Ahmed, M. M., Shamim, M. S.,
Mamun, S. A. and Ganguly, A. A Traffic-Aware Medium
Access Control Mechanism for Energy-Efficient Wireless
Network-on-Chip Architectures. arXiv preprint
arXiv:1809.07862, 2018.
Chang, K., Deb, S., Ganguly, A., Yu, X., Sah, S. P., Pande,
P. P., Belzer, B. and Heo, D., Performance evaluation and
design trade-offs for wireless network-on-chip architectures.
ACM Journal on Emerging Technologies in Computing
Systems (JETC), 2012. 8(3): 23.
Deb, S., Sah, S. P., Cosic, M., Chang, K., Yu, X., Heo, D.,
Ganguly, A., Belzer, B. and Pande, P. P., Design of an energy
efficient CMOS compatible NoC architecture with
millimeter-wave wireless interconnects. IEEE Transactions
on Computers, 2012. 99(1).
Deb, S., Ganguly, A., Pande, P. P., Belzer, B. and Heo, D.
Wireless NoC as interconnection backbone for multicore
chips: Promises and challenges. IEEE Journal on Emerging
and Selected Topics in Circuits and Systems, 2012. 2(2):
–239.
Dally, W. J. and Towles, B. Route packets, not wires: On-
chip interconnection networks. Design Automation
Conference, 2001. Proceedings. IEEE. 2001. 684–689.
Abadal, S., Mestres, A., Torrellas, J., Alarcón, E. and
Cabellos-Aparicio, A. Medium Access Control in Wireless
Network-on-Chip: A Context Analysis. IEEE
Communications Magazine, 2018. 56(6): 172–178.
Qian, Z., Abbas, S. M. and Tsui, C.-Y. Fsnoc: A flit-level
speedup scheme for network on-chips using self-
reconfigurable bidirectional channels. IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, 2015.
(9):1854–1867.
Kannan, A., Jerger, N. E. and Loh, G. H. Enabling
interposer-based disintegration of multi-core processors.
Microarchitecture (MICRO), 2015 48th Annual IEEE/ACM
International Symposium on. IEEE. 2015. 546–558.
Ganguly, A., Ahmed, M. M., Singh Narde, R., Vashist, A.,
Shamim, M. S., Mansoor, N., Shinde, T., Subramaniam, S.,
Saxena, S., Venkataraman, J. et al. The Advances, Challenges
and Future Possibilities of Millimeter-Wave Chipto-Chip
Interconnections for Multi-Chip Systems. Journal of Low
Power Electronics and Applications, 2018. 8(1):5.
Kim, K., Floyd, B., Mehta, J., Yoon, H., Hung, C.-M.,
Bravo, D., Dickson, T., Guo, X., Li, R., Trichy, N. et al. The
feasibility of on-chip interconnection using antennas.
Proceedings of the 2005 IEEE/ACM
International conference on Computer-aided design, IEEE
Computer Society 2005, 979–984.
Murugesan, R. Artificial Neural Network Based Prediction
Mechanism for Wireless Network on Chips Medium
Access Control. 2017.
Gholipour, M., Haghighat, A. T. and Meybodi, M. R. Hop-
by-hop trafficaware routing to congestion control in wireless
sensor networks. EURASIP Journal on Wireless
Communications and Networking, 2015. 2015(1): 15.
Mansoor, N., Iruthayaraj, P. J. S. and Ganguly, A. Design
methodology for a robust and energy-efficient millimeter-
wave wireless network-on-chip. IEEE Transactions on
Multi-Scale Computing Systems, 2015. 1(1): 33–45.
Mishra, A. K., Vijaykrishnan, N. and Das, C. R. A case for
heterogeneous on-chip interconnects for CMPs. ACM
SIGARCH Computer Architecture News. ACM. 2011,
vol. 39. 389–400.
Mansoor, N., Shamim, M. S. and Ganguly, A. A demand-
aware predictive dynamic bandwidth allocation mechanism
for wireless network-on-chip. Proceedings of the
th System Level Interconnect Prediction Workshop.
ACM. 2016. 8.
Narayana, S. A. An artificial neural networks based
temperature prediction framework for network-on-chip based
multicore platform. arXiv preprint arXiv:1612.04197, 2016.
Monemi, A., Ooi, C. Y. and Marsono, M. N. Low latency
network-onchip router microarchitecture using request
masking technique. International Journal of Reconfigurable
Computing, 2015. 2015: 2.
Wu, D., Al-Hashimi, B. M. and Schmitz, M. T. Improving
routing efficiency for network-on-chip through contention-
aware input selection. Proceedings of the 2006 Asia and
South Pacific Design Automation Conference. IEEE Press.
36–41.
Jantsch, A., Tenhunen, H. et al. Networks on chip. vol. 396.
Springer. 2003. 60. Bell, S., Edwards, B., Amann, J.,
Conlin, R., Joyce, K., Leung, V., MacKay, J., Reif, M., Bao,
L., Brown, J. et al. Tile64-processor: A 64-core soc with
mesh interconnect. Solid-State Circuits Conference, 2008
ISSCC 2008. Digest of Technical Papers. IEEE International,
IEEE, 2008. 88–598.
Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H.,
Tschanz, J., Finan, D.,Iyer, P., Singh, A., Jacob, T. et al. An
-tile 1.28 TFLOPS network-on-chip in 65nm CMOS
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest
of Technical Papers. IEEE nternational. IEEE. 2007. 98–589.
Bjerregaard, T. and Mahadevan, S. A survey of research
and practices of network-on-chip. ACM Computing Surveys
(CSUR), 2006. 38(1): 1.
Amorim, A. M., Oliveira, P. A. and Freitas, H. C.
Performance evaluation of single-and multi-hop wireless n
Networks-on-chip with NAS Parallel Benchmarks. Journal
of the Brazilian Computer Society, 2015. 21(1): 6.
Hagglund, T. and Astrom, K. PID controllers: theory,
design, and tuning. ISA-The Instrumentation, Systems, and
Automation Society, 1995. 140. Salihundam, P., Jain, S.,
Jacob, T., Kumar, S., Erraguntla, V., Hoskote, Y., Vangal, S.,
Ruhl, G. and Borkar, N.A2 Tb/s 6X4 Mesh Network for a
Single-Chip Cloud Computer With DVFS in 45 nm CMOS.
IEEE Journal of Solid-State Circuits, 2011. 46(4): 757–766.
Guerrier, P. and Greiner, A. A generic architecture for on-
chip packet-switched interconnections. Design,
Automation and Test in Europe. Springer. 2008. 111–123.
Salihundam, P., Jain, S., Jacob, T., Kumar, S., Erraguntla,
V., Hoskote, Y., Vangal, S., Ruhl, G. and Borkar, N. A 2
Tb/s 6X4 Mesh Network for a Single-Chip Cloud Computer
With DVFS in 45 nm CMOS. IEEE Journal of Solid-State
Circuits, 2011. 46(4): 757–766.
Downloads
Published
How to Cite
Issue
Section
License
Copyright of articles that appear in Elektrika belongs exclusively to Penerbit Universiti Teknologi Malaysia (Penerbit UTM Press). This copyright covers the rights to reproduce the article, including reprints, electronic reproductions, or any other reproductions of similar nature.
