Fault Injection Test on Error Mitigated Circuit of Partial TMR in FPGA

Abstract

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEU), affecting the reliability of embedded system devices. Triple Modular Redundancy (TMR) has been proposed in the literature to mitigate error within the configuration memory of an SRAM-based FPGA. In this paper, TMR and Partial TMR were compared through an FPGA development board of DE1- SoC (System on Chip). Fault modules are inserted in the architecture to emulate fault injection on the circuit under test (CUT). The result from the fault injection test shows that TMR gave a 50% passing rate, whereas Partial TMR gave an additional 16.67% passing rate on top of normal TMR.