Low-Power Self-Biased Widlar Current Source for Sub-µA Biomedical Applications in 0.25 µm CMOS Technology

Abstract

This paper provides a systematic investigation of transistor sizing strategies for a self-biased Widlar current mirror topology to evaluate performance tradeoffs between subthreshold and saturation operation, focusing on ultra low current (< 1uA) bias generation suitable for biomedical applications. The first design (D1) employs aspect ratios that ensure all transistors operate in the subthreshold region, while the second design (D2) uses sizing that places all transistors in saturation. All simulations were performed using Eldo in Tanner EDA S-Edit environment, utilizing a 0.25 µm CMOS process. Simulation results confirm that both configurations generate output currents below 1 µA, making them suitable for low-power analog and biomedical circuits. The total power consumption for D1 is 3.5090 µW and for D2 is 3.5217 µW. D1 exhibits superior current matching and minimal temperature drift, whereas D2 achieves a higher PSRR (−71 dB), indicating stronger noise immunity. These results show that by adjusting the aspect ratio based on topology can help improve low-power current references despite changes in process, voltage, and temperature.